1. Field of the Invention
This invention relates to a semiconductor memory device. More particularly, the present invention relates to a semiconductor memory device capable of limiting the voltage amplitude on an input/output line (I/O line) by utilizing an amplitude limiting means comprising a current load, or the like.
2. Description of the Related Art
In a semiconductor memory device 1, a method which reads out data or information, from a cell 6 and amplified by a sense amplifier 2, to input/output line, that is, an I/O line pair 4, in which an I/O amplifier (AMP) 7 is provided, through a column line CL inclusive of a transfer gate 3 consisting of a column gate, etc., has been employed in the past, as shown in FIG. 8.
The demand for higher speed performance from the semiconductor memory device 1 having the above construction has increased in recent years. According to the prior art, the read operation for new data is carried out after a short reset operation is made whenever data, from the cell 6 in a cell array 66 and amplified by the sense amplifier, is individually read out. For this reason, the data readout operation requires time, and this is a problem for high speed performance.
In other words, in the semiconductor memory device 1 shown in FIG. 8, reset means 5' is provided to the I/O line pair 4, and whenever the data from the cell 6 in the cell array 66 amplified by the sense amplifier 2 is read out, the short reset operation is conducted and then the new data is read out. Accordingly, the data readout time is long and this is a problem for attaining a high operation speed.
More concretely, FIG. 9 shows the output waveform in the semiconductor memory device shown in FIG. 8.
Referring to FIG. 9, when a driving signal Sdrv of the sense amplifier 2 changes simultaneously with the change of a word line WL, a potential difference is generated between column lines CL and/CL (CL bar), and then a column decoder 1 (CD1) is selected and activated. Therefore, a predetermined potential difference is generated between the I/O line pairs 4-1 and 4-2, and in the mean while, the driving signal Samp of the I/O amplifier (AMP) 7 rises.
However, after the column decoder 1 (CD1) enters the non-selected state, the resent means 5' outputs the reset signal (Rset) before the column decoder 2 (CD2) is subsequently selected afresh, and the short reset operation is executed.
On the other hand, as a method of improving the conventional example described above, a semiconductor memory device 1 shown in FIG. 5 is known. Namely, this is the semiconductor memory device having basically the circuit construction shown in FIG. 8, wherein amplitude limiting means 5 comprising a current load, etc., is disposed so as to provide a suitable potential difference between the I/O line pair lest the information such as the data stored in the cell 6 is destroyed when the data of the cell 6 amplified by the sense amplifier 2 is read out to the input/output lines, that is, the I/O line pair 4, through the column line CL inclusive of the transfer gate 3 consisting of the column gate, etc.
In other words, in place of the short reset operation system according to the prior art, each of the I/O line pair 4 is connected to a power supply line through a transistor, and predetermined data is read out while the amplitude of the voltage applied to this I/O line pair is limited, as shown in FIG. 5.
In the semiconductor memory device having the current load system described above, when a voltage higher than a set value is applied to each line in the I/O line pair, for example, the data read out is destroyed when the data stored in each cell 6 of the cell array 66 is read out.
FIG. 10 is a graph showing the output waveform in another conventional example shown in FIG. 5.
In FIG. 10, when the driving signal Sdrv of the sense amplifier 2 changes simultaneously with the change of the word line WL in the same way as in FIG. 9, the potential difference is generated between the column lines CL and/CL (CL bar) but thereafter, the control signal (LON) of the amplitude limiting means 5 rises, unlike in FIG. 9, and at the same time, the column decoder 1 (CD1) is selected and rises, so that a predetermined potential difference is generated between the I/O line pair 4-1 and 4-2.
In the example shown in FIG. 10, however, the potential difference between the I/O line pair 4-1 and 4-2 is considerably smaller than the potential difference in FIG. 9.
After the column decoder (CD1) enters the non-selected state in the same way as in FIG. 9, the potential difference between the I/O line pair 4-1 and 4-2 is kept substantially constant and is detected during the time in which the column decoder 2 (CD2) is again selected.
In other words, in the concrete example shown in FIG. 5, the operation speed becomes faster to the extent corresponding to non-execution of the short reset operation, and an erroneous operation might occur unless the amplitude is limited to a certain value. Another problem is that if the amplitude is excessively limited to a low level, the data cannot be read out.
In the prior art devices, therefore, the capacity of the sense amplifier 2, the I/O line pair 4 and the transfer gate (column gate) 3 for connecting them has been strictly set lest the data read out from the cell is destroyed, and design is made so that the sense amplifier, the I/O lines and the I/O amplifier 7 keep a predetermined balance.
In other words, the semiconductor memory device according to the prior art described above is equipped with the amplitude limiting means 5 comprising the current load, etc., for limiting the voltage applied to the I/O lines or the potential difference between the I/O line pair 4 to a level at which the data read out is not destroyed. Because this amplitude limiting means 5 limits the current value flowing through the I/O lines 4, the voltage amplitude between the I/O line pair 4 is limited to a predetermined value.
However, even such a semiconductor memory device is not free the following problem. Namely, when a resistance component is parasitically coupled with the transfer gate 3 or with the column line CL, for example, or when any noise is contained in the input signal, dullness occurs in a part of the waveform N as shown in FIG. 7 and a skew occurs between the output waveform of the column line CL of the next stage, although, in the normal case, substantially the same waveform appears in accordance with the address signal and the "H" level and the "L" level repeat, as shown in FIG. 6.
In such a case, if the threshold value Vth of the transistor constituting the column gate 3 overlaps with the N portion as shown in FIG. 7, multiple selection occurs between the column gate of the preceding stage and the column gate 3 of the next stage and results in the erroneous operation. When such a multiple selection occurs in the column gate corresponding to a plurality of cells, the potential difference between the I/O line pair becomes very large, and the balance between the current supply capacity of this current load 5 and the current capacity of the sense amplifier disappears so that the amplitude of the I/O lines becomes large.
When the amplitude of the I/O line pair becomes large, a larger current is allowed to flow from the I/O lines and the amplitude can be limited, but when the current quantity becomes large, the cell data will be destroyed.